Pulse motor drive systems

ABSTRACT

The pulse motor drive system comprises a plurality of flip-flop circuits connected in an endless chain, each of the flip-flop circuits including a pair of input terminals and a pair of output terminals. At least one output terminal of each flip-flop circuit is connected to the input terminals of the flip-flop circuits on both sides thereof through gate circuits. The initial state of output signals for output terminals of all flip-flop circuits are determined by a reset signal and the state thus determined is shifted one by one by trigger pulses. Output conductors are connected between output terminals of every other flip-flop circuits and a conventional pulse motor to energize coils thereof in a predetermined order.

United States Patent [72] Inventor Kunihiko Eto Kariya-shi, Japan [21] Appl. No. 888,644 [22] Filed Dec. 29, 1969 [45] Patented Oct. 19, 1971 [73] Assignee Toyoda Koki Kabushiki Kaisha Aichi-ken, Japan [32] Priority Dec. 29, 1968 [33] Japan [31] 43/795/69 [54] PULSE MOTOR DRIVE SYSTEMS 4 Claims, 7 Drawing Figs. [52] U.S. Cl 318/696, 307/223 [51] Int. Cl G051) 19/40 [50] Field of Search 307/223; 318/138, 234, 696, 685; 328/106 [56] References Cited UNITED STATES PATENTS 3,112,433 11/1963 Fairbanks 318/138X Primary Examiner-G. R. Simmons Attorney-Ward, McElhannon, Brooks & Fitzpatrick ABSTRACT: The pulse motor drive system comprises a plurality of flip-flop circuits connected in an endless chain, each of the flip-flop circuits including a pair of input terminals and a pair of output terminals. At least one output terminal ofeach flip-flop circuit is connected to the input terminals of the flipflop circuits on both sides thereof through gate circuits. The initial state of output signals for output terminals of all flipflop circuits are determined by a reset signal and the state thus determined is shifted one by one by trigger pulses. Output conductors are connected between output terminals of every other flip-flop circuits and a conventional pulse motor to energize coils thereofin a predetermined order.

PATENTEnncnssen SHEETZUF 3 Fig. 2

V0000 l411100 w 10000 m 1 1 1 1 1 0 0 O 0 1 I 00000111 000001 1114! m3 7 Mwm mwia wa wiaew w mmmwwmwwwwww T mm mm 0000011111 0000 1100 nwooo llllooo 0000 AW 0 1 1 1 1 1 O O 0 0 O nu 000001 Am 1 1 1 1 0 O O 0 0 1 1 nn 00000111 nr 1 1 0 O 0 O 0 1 1 1 1 0 000 001 1 1 t Mmmu n uJza4i$J w w F wmwwwwwmwmmw =4 Fig. 5

Fig. 4

PULSE MOTOR DRIVE SYSTEMS This invention relates to a novel pulse motor drive system for controlling the direction of rotation thereof by means of flip-flop circuits and gate circuits.

It is an object of this invention to provide a novel pulse motor drive system to control the direction of rotation thereof by alternately energizing mphase coil or coils and (m-l-I) phase coils of the motor, where mrepresents a natural number selected such that (2m+l) is equal to the number of phase coils of the pulse motor.

Another object of this invention is to provide a pulse motor drive system which readily enables to change the direction of rotation of the motor from forward to reverse or vice versa.

Still another object of this invention is to provide an improved pulse motor drive system which is reliable in operation and simple in construction.

To accomplish these and other objects in accordance with this invention, a plurality of identical flipflop circuits are connected in an endless chain, each flip-flop circuit being provided with an input terminal, a complementary input terminal, an output terminal, and a complementary input terminal. The output terminal or both output terminals of each one of the flip-flop circuits are connected to both input terminals, i.e. input tenninals and complementary input terminals of the flipfiop circuits situated on both sides thereof. Conductors of lead wires are connected to the output terminals of every other flip-flop circuits so as to energize selected coils of the pulse motor in a predetermined order. A reset signal operates to set a first half of flip-flop circuits and to reset a second half of the flip-flop circuits so that the former produces binary output signals l at respective output terminals and the latter produces binary output signals at respective output terminals; Ever trigger pulse operates to reverse one flip-flop circuit in the first half and one flip-flop circuit in the second half in such a manner that successive halves of the flip-flop produce signals 1 at the output terminals while the other successive halves produce signals 0 at the output terminals.

In the accompanying drawings:

FIG. I is a block diagram of a first embodiment of a pulse motor drive system embodying this invention;

FIG. 2 is a chart showing output signals provided by respective flip-flop circuits in the pulse motor drive system when forward drive signals are applied thereto;

FIG. 3 is a chart showing output signals supplied to the pulse motor when forward drive signals are applied to the pulse motor drive system shown in FIG. 1;

FIG. 4 is a chart showing output signals provided by respective flip-flop circuits in the pulse motor drive system shown in FIG. I when reverse drive signals are applied thereto;

FIG. 5 is a similar chart showing output signals supplied to the pulse motor when reverse drive signals are applied to the pulse motor drive system shown in FIG. 1;

FIG. 6 shows a longitudinal section of a conventional pulse motor driven by the pulse motor drive system shown in FIG. I; and

FIG. 7 shows a block diagram of a second embodiment of the pulse motor drive system embodying this invention.

Generally, the present invention relates to a pulse motor drive system adapted to control a pulse motor provided with n stators and n rotor blocks which are individually magnetized by respective coils where n is a natural number equal to three or more.

Referring now to FIG. I of the accompanying drawings, there is shown a first embodiment of a pulse motor drive system of this invention adapted to control the direction of rotation of a conventional motor provided with five coils, five rotor blocks and five pairs of stators as shown in FIG. 6 wherein two coils and three coils are alternately energized to provide a half-pitch drive. Flip-flop circuits FF through FF inclusive are provided with output terminals 0, thorughQ complementary output terminals 6, through 6, input terminals .I, through I-l,,, complementary input terminals K, through Km Set terminals SD, through 8D,, reset terminals RD, through RD and trigger terminals T, through T,,,

respectively. Each of these flip-flop circuits has the same construction and operates identically. For the sake of brevity, hereinafter it is referred toas a J K flip-flop." The operation of the .I-K flip-flop will be described with reference to the first J-K flip-flop FF, This J-K flip-flop FF, generates output l and 0 at the respective output terminals 0, and 6, when a trigger pulse is applied to trigger terminal T, where input signals l and 0 are being applied to input terminals J, and K,, respectively. The first .I-K flip-flop FF, also generates outputs 0" and l at output terminals 0, and 6,, respectively, in response to the application of a trigger pulse to trigger terminal T, where input signals 0" and l are being applied to input terminals J, and l(,, respectively. Furthermore, when input signals are not applied to both input terminals J, and K, the first .I-K flip-flop will not change the outputs from output terminals Q, and 6, even if a trigger pulse is applied to trigger terminal T,. In this specification input and output signals, etc. are represented by a binary code system so that a higher or significant voltage and a lower or zero voltage are expressed by a binary I and a binary 0," respectively. A forwardsignal input conductor F for passing forward drive signals is connected to input terminals la, 30, 5a; 7a, 9a, Ila, 13a, 15a, 17a and 19a of respective NAND circuits 12A, 14A, l6A,'l8A, 20A, 22A, 24A, 26A, 28A, and 30A. Forward signal input conductor F is also connected to input terminals lb 3b, 5b 7b, 9b, 11b, 13b, 15b, 17b and l9b of respective NAND circuits 12B, 14B, 16B, 18B, 20B, 22B, 24B, 26B, 28B and 30B. Input terminals la, 3a, 5a, 7a, 9a, Ila, 13a, 15a, "41 and 19a and input terminals b, 3b, 5b, 7b, 9b, 11b, 13b, 15b, 17b and 1% are referred to as odd input terminals. The NAND circuits 12A, 14A, 16A, 18A, 20A, 22A, 24A, 26A, 28A and 30A and NAND circuits 12B, 14B 16B, 18B, 20B, 22B, 26B, 28B and 30B are herein referred to as AE-NAND circuits and BE- NAND circuits, respectively. The terms odd, AE" and "BE" do not have any significant meanings but are used to distinguish them from each other. A reverse signal input conductor R for passing reverse drive signals is connected to input terminals 2a'4a '6a8a'l0a'l2a14al6al8aand 20a'of NAND circuits 11A, 13A, 15A, 17A, 19A, 21A, 23A, 25A, 27A and 29A, respectively. Input conductor R is further connected to input terminals 2b'4b'6b8b 'l0b'l2bl4b'l6b'l8b'and 20bof respective NAND circuits 11B, 13B, 15B, 17B, 19B, 21B, 23B, 25B, 27B and 29B. Input tenninals 2a'4a'6a'8a'l0a 12a 14a 16a 18a and 20a; 2b,4b",6b'tIQ1glgf12B1l4b'16b' 18b, and 20b; NAND circuits 11A, 13A, 15A, 17A, 19A, 21A, 23A, 25A, 27A, and 29A; and NAND circuits IIB, 13B, 15B, 17B, 19B, 21B, 23B, 25B, 27B and 29B are hereinafter referred to as even input terminals," AU-NAND circuits and BU-NAND circuits," respectively. Again the "even," do not have any significant meanings but are used to distinguish them from each other. Each one of all AE, AU, BE and BU-NAND circuits having quite identical operation and construction produces signals "0" only at the time when signals l are applied simultaneously to their even and odd terminals whereas each produces signals I when a signall is applied to their even orodd input terminals or when signals I are not applied to both of their input terminals.

Output terminals provided for the AE-NAND circuits are respectively connected to input terminals A,, A, A,, A, A, A, A, A, A, and A,,, of AND circuits l-A, 2A, 3A, 4A, 5A, 6A, 7A, 8A, 9A and 10A which are herein termed as A-AND circuits. Output terminals provided for AU-NAND circuits are also connected to input terminals A,'A,'A, A, A, A,,', A, "138, A,,' and A,,, of the ;A-Alfll) ggcuits respectively. Output terminals provided for BE and BU-NAND circuits respectively connected to input terminals B, B, B, B, B, B, B, B, B, and B and to input terminals B, 'B,'B, B, 'B, B, 'B, B, B,and B,,,', of AND circuits 1B, 2B, 3B, 4B, 5B, 6B, 7B, 8B, 9B, and 10B which are termed as B-AND circuits hereinafter. Output terminals of A-AND circuits and B-AND circuits are respectively connected to input terminals K,, K, K, K, K, K, K, K, K, and K, and to the input terminals J, J, ,1,

Q J, J, J, J, J, and J ofJ-K flip-flops FF, FF FF, l-F FF, FF, FF, FF FF and FF,,,. All A and B-AND circuits have identical construction and produce output signals 1 only when signals 1 are applied simultaneously to both of their input terminals. Output terminals -Q, Q Q Q Q5 Q; Q1 Q8 Q9 and Q of .l-K flip-flops are connected to the even input terminals 4a 6a, 8a, 10a, 12a, 14a, 16a, 18a, 20a and 2a of AE-NAND circuits, respectively. These even input terminals are also connected to odd input terminals 19a, la, 3a, 5a, 7a, 90', 11a, 13a, 15a" and 17a of AU-NAND circuits, respectively. The output terminals or gm plernent ry output terminals 6,, 6 6 6 6 66, 61, 0,, Q, and 0,. of J-K flip-flops are respectively connected to even input tenninals 4b, 6b, 8b, 10b, 12b, 14b, 16b, 18b, 20b and 2b of the BE-circuits, these complementary outputs being also connected to odd input terminals 19b, lb, 3b, 5b, 7b, 9b, 11b, 13b, 15b and 17b of the BU-NAND circuits, respectively.

A reset signal input conductor Re for passing reset signals is connected to set terminals 8D,, 8D,, 5D,, SD, and SD, of .l-K flip-flops FF,, FF,, FF FF, and FF,, respectively and also to reset terminals RD RD RD,, RD, and RD of the J-K flipflops FF FF,, FF,,, FF, and FF,,,.

A trigger pulse input conductor T for passing trigger signals or pulses is connected to trigger terminals T,, T T T T T T,, T,,, T, and T, of J-K flip-flops, respectively. Output terminals Q,, Q,,, 0,, Q, and Q are further connected to a conventional pulse motor through output conductors I, II, III, IV and V. These conductors are connected to respective coils 101, 102, 103, 104, and 105 of the pulse motor through respective amplifiers 401, 102, 103, 404 and 405, as shown in FIG. 6. The illustrated pulse motor comprises a housing 501, five pairs of stators 201a and 20lb 202a, and 202b, 203a and 203b, 2040 and 204b, 2050 and 205b which are secured to the housing, five cylindrical wound coils 101, 102, 103, 104, and 105 interposed between respective stator pairs and a rotor including five rotor blocks 301, 302, 303, 304 and 305 which are magnetically isolated from each other and are mounted on a shaft 502 rotatably journaled by housing 501.

Upon application of a reset pulse on reset conductor Re, J- K flip-flops FF,, FF,, FF FF,, and FF, are set and the other .I- K flip-flops F F,,, FF-,, F F,,, F F, and FF are reset. In the set and reset conditions, output signals :1" are generated at output terminals 01, Q2 Q3, Q4, Q5, 66, Q1, 65, 69 and 610 OfJ-K fl ptlops FF, through FF inclusive and output signals 0 are generated at output terminals 6|, 6:, 6a, 4, 65, Q6, Q1, Q8, Q9 and Q10 of these flip-flops. Thus, output signals 1 at output terminals 0,, Q, and Q, are applied to three coils 101, 102 and 103 respectively through output conductors I, ll and ill whereby these three coils are energized to magnetize three pairs of the stators 201a and 201b, 2020 and 202b, 203a and 203b and three rotor blocks 301, 302 and 303 corresponding to said three pairs of the stators. Furthermore, output signals :l appearing at output terminals 0,, Q Q Q Q 6,, 6 Q,,, 6, and 6, are furnished to even input terminals 40, 6a, 80, a and 12a of the even AE-NAND circuits and to even input terminals 14b, 16b, 18b, 20b and 2b of the BE-NAN D circuits and thence to odd input terminals l9a',la', 3a, Saand 7a of the AU-NAND circuits and to the odd input terminals 9b 1 lb, 13b, b and 17b of the BU-NAND circuits. However, in the set and reset con i itigr rs, t he input terminals connected to output terminals 6n Q2 Q3, Q4, ,6! Q5 Q? on, Q9 and Q10 i.e. even input terminals 4b, 6b, 8b, 10b, and 12b of the BE- NAND circuits, the odd input terminals 19b, lb, 3b, 5b and 7b of the BU-NAND circuits, even input terminals 14a, 16a, 18a, 20a and 2a of the AE-NAND circuits and odd input terminals 9a, 11a, 13a, 15a and 17a of the AU-NAND circuits, are not supplied with any significant electric voltage so that output signals "0" or no significant voltage are generated thereat. Thus, A-AND circuits 1A, 2A, 3A, 4A, 5A, 6A, 7A, 8A, 9A and 10A generate output signals l" which are applied to input terminals K,, K,, K,, K K K K K K and K of the J-K flip-flops since both of all AU-NAND circuits and all AE-NAND circuits generate output signals 1" since they are not simultaneously supplied with signals l at their even and odd input terminals.

B-AND circuits 1B, 2B, 3B, 4B, 5B, 6B, 7B, 8B, 9B and 108 also generate signals 1" which are supplied to input terminals 1, through J inclusive of .l-K flip-flops since both of all BU- NAND circuits and BE-NAND circuits generate output signals 1" since they are not simultaneously supplied with signals l at their even and odd input terminals.

When an input signal 1" and an input signal 0" are applied to forward signal input conductor F and to reverse signal input conductor R, respectively, the input signal l is furnished to the odd input terminals of AE-NAND circuits 12A, 14A, 16A, 18A, 20A, 22A, 24A, 26A, 28A, and 30A and of BE-NAND circuits 12B, 14B, 16B, 18B, 20B, 22B, 24B, 26B, 28B and 308 through forward signal input conductor F, and input signal 0" is furnished to the even input terminals ofAU-NAND circuits 11A, 13A, 15A, 17A, 19A, 21A, 23A, 25A, 27A and 29A and of BU-NAND circuits 11B, 13B, 15B, 17B, 19B, 21B, 23B, 25B, 27B and 293 through reverse signal input conductor R. Accordingly, AE-NAND circuits 14A, 16A, 18A, 20A and 22A and BIS-NAND circuits 24B, 26B, 28B, 30B and 12B generate signals 0" since these NAND circuits are simultaneously supplied with signals 1 "to their even and odd input terminals. Remaining NAND circuits, i.e. all AU-NAND circuits and BU-NAND circuits, AE- NAND circuits 24A, 26A, 28A, 30A and 12A and BE-NAND circuits 14B, 16B, 18B, 20B, 22B of the BE-NAND circuits, generate output signals l since they are not simultaneously supplied with signals l" at both of their input tenninals. Therefore A-AND circuits 2A, 3A, 4A, 5A and 6A and B- AND circuits 7B, 8B, 98, 10B and 1B generate signal 0" and A-AND circuits 7A, 8A, 9A, 10A and 1A and B-AND circuits 2B, 3B, 4B, 5B, and 6B generate signals l" to apply the signals I to the input terminals l(,, 1 J J J 1,, K,, K,,, K, and K, of respective flip-flops FF,, FF FF FF,, FF F F FF FF,,, FF, and FF and to apply signals 0" to input terminals .l,, K K K K K 1,, J J and 1,, thereof.

When a forward trigger pulse No.- l (the term forward trigger pulse means a trigger pulse applied to trigger input conductor T when a forward signal is applied to forward signal input conductor F) is applied to trigger input terminals T,

through T inclusive J-K flip-flops FF, and FF, are switched or reversed thus generating output signals l at output terminals 6, and 0, instead of output tenninals Q, and Q, But the other J-K flip-flops FF,, FF,,, FF,, FF FF FF,,, FF, and FF are maintained in their previous state i.e. .I-K flip-flops FF Ff,,, FF, and FF, are supplied with input signals l at their input terminals 1,, 1,, J, and J, to produce output signals l at their output terminals Q Q,,, Q, and Q and J-K flipflops FF,, FF,,, FF, and FF are supplied with input signals l at their input terminals K,, K,,, K, and 5, to produce output signals 1 at their output terminals 0,, 2,, 6,, and 6,,,. Thus, output signals 1" to be supplied to the electric pulse motor are obtained at conductors ii and ill connected to output terminals Q and 0,, thus energizing coils 102 and 103. As the result, the signal 0 from output terminals Q, is supplied to odd input terminal 19a of AU-NAND circuit 29A and to even input terminal 4a of AE-NAND circuit 14A. As a result, NAND circuit 14A changed its output signal from 0 to l since only a single signal 1" is supplied to the odd input terminal 3a from forward input conductor F. Thus, A-AND circuit 2A supplies a signal l to input terminal K,, since AU- NAND circuit 13A continues to supply a signal l "to A-AND circuit 2A. On the other hand, a signal 1" from output terminal 6, is supplied to even input terminal 19b of BU-NAND circuit 298 and to even input tenninal 4b of BE-NAND circuit 148 whereby NAND circuit 148 changes its output signal from 1" to 0 since a signal l is supplied to odd input terminal 3b from the forward signal input conductor F. Thus B- AND circuit 28 supplies a signal 0" to input terminal J, since NAND circuit 138 continues to produce a signal l Similarly, as a result of the reversal of J-K flip-flop F F, a signal 1 from output terminal 6, is supplied to odd input terminal 9a of AU-NAND-circuit 19A and to even input terminal 14a of AE-NAND circuit 24A causing this AE-NAND circuit 24A to change its output signal from l to since the odd input terminal 13a of AE-NAND circuit 24A (after 0") is supplied with a signal 1" from forward input conductor F. Thus A- AND circuit 7A supplied a signal "0 to input terminal K, since the output of AU-NAND circuit 23A is still 0. On the other hand, the signal 0 from output terminal 6, is supplied to odd input terminal 9b of BU-NAND circuit 198 and to even input terminal 14b of BE-NAND circuit 248 thus causing BE-NAND circuit 248 to change its output signal from 0" to 1". Thus, B-AND circuit 78 supplies a signal 1 to input terminal J, since odd input terminal 13b is supplied with a signal 1" from forward input conductor F and the output signal of BU-NAND circuit 238 is still 1." In brief, forward trigger'pulse No. 1 switches or reverses flip-flops FF, and FF, and as a result of the reversal of .l-K flip-flop FF,, the output signal from A-AND circuit 2A is changed from 0 to 1" whereas the output signal from B-AND circuit 28 is changed from l to "0" whereby input terminal K, receives a significant voltage, i.e. signal l instead of input terminal 1,. In the same manner, input terminal J, of .I-K flip-flop FF, receives a signal 1 "instead of its input terminal K When the operation caused by the forward trigger pulse No. 1 has been completed a forward trigger pulse No. 2 is applied to the pulse motor drive system embodying this invention. Upon application of the forward trigger pulse No. 2 to trigger terminals T, through T, inclusive through input trigger conductor T, J-K flip-flops FF, and FF, will be reversed so as to generate output signals 1" at their output terminals 6, and Q, respectively. However, the other flip-flops FF,, FF,, FF,, FF FF FF,, FF, and FF, are maintained in their previous state i.e. .l-K flip-flops FF F F,, FF and F F, are furnished with input signals 1" at their input terminals J J J,and J to produce output signals 1 at their respective output terminals 0,, 0., Q, and Q, and .l-K flip-flops FF,, FF,, FF and FF, are supplied with input signals 1" at their input terminals K,, K,, K, and K, to produce t itput signals 1" at their output terminals 6,, 6,, 6, and 0,, respectively. Thus, output signals l are supplied to the elective pulse motor from output conductors ll, 11! and IV connected to output terminals Q, Q, and Q,, thus energizing coils 102, 103 and 104. As a result of the reversal of the .l-K flip-flop FF,, the signal supplied from A-AND circuit 3A to input terminal K, of J-K flip-flop FF, is changed from 0" to 1 since the output signal of AU- NAND circuit A is still 1 and the output signal of AE- NAND circuit 16A is changed from 0 to 1 by the change of output signal 0 from the output terminal Q, to the even input terminal 6a. On the other hand, the signal supplied to input terminal J, of .l-K flip-flop FF, from B-AND circuit 38 is changed from 1 to 0 since the output signal of BU-NAND circuit 158 is still l and the output signal of BE-NAND circuit 168 has been changed from l to 0 due to the change in the output signal 1 from the output terminal 6, to even input terminal 6b of BE-NAND circuit 168.

Similarly, as a result of the reversal of J-K flip-flop FF,, the signal supplied from A-AND circuit 8A to input terminal K, of .l-K flip-flop FF, is changed from 1" to 0" since the output signal of AU-NAND circuit A is still 1" whereas the output of AE-NAND circuit 26A has been changed from 1" to 0 since both even and odd input terminals 15a and 16a of NAND circuit 26A are supplied with signals 1" from output terminal 0, and forward input conductor F, respectively. On the other hand the output signal of B-AND circuit 83 supplied to input terminal J, of .l-K flip-flop FF, is changed from 0 to l since the output terminal of BU-NAND circuit 258 is still l and the output signal of BE-NAND circuit 268 has been changed from 0 to 1" because odd input terminallSb is supplied with a signal "1 from forward input conductor F while input terminal 16b with a signal 0" from output terminal 6,. Accordingly, when .l-K flip-flops FF, and FF, are reversed by the action of a forward trigger pulse No. 2, their input terminals which are applied with signals 1" will be changed from J, to K, and from K, to J,, respectively.

Upon completion of the operation caused by the trigger pulse No. 2 a forward trigger pulse No. 3 is supplied to the pulse motor drive system of this invention. When a trigger pulse No. 3 is applied to trigger input terminals T, through 1",, inclusive, .l-K flip-flops FF, and FF, are reversed in the same manner as has been described in connection with forward trigger pulse No. l and No. 2 whereby the output terminals for producing signals 1" are switched from Q, to 6, and from 6, to 0,, respectively. Therefore, output signals l supplied to the pulse motor are obtained on output conductors Ill and 1V to energize coils 103 and 104 and the input terminals of MC flip-flops FF and FF, which are supplied with the signal l are changed from J, to K, and from K,to J, to prepare J-K flipflops FF, and F F, for the reversal caused by a forward trigger pulse No. 4.

In this manner, two J-K flip-flops are reversed by a forward trigger pulse so that each of two other J-K flip-flops immediately to the right of said first-mentioned two flip-flops are switched to other state to receive signals 1 to prepare for a next forward trigger pulse. Therefore, while a signal 1" is being applied through forward signal input conductor F, when forward trigger pulses No. 1 through No. 10 inclusive are successively applied to trigger input terminals T, through T inclusive of the J-K flip-flops, the output signals from output terminals Q, through 0,, inclusive will change according to the first chart shown in FIG. 2. As will be noted from the first chart output signals from respective output terminals caused by a forward trigger pulse No. 10 are the same as in the initial condition, that is the reset condition. Therefore, when the next trigger pulse or a forward trigger pulse No. 11 is applied to respective trigger input terminals subsequent to forward trigger pulse No. 10, then output signals from output terminals 0, through 0,, inclusive will be changed to the same conditions as when trigger pulse No. l was applied.

As long as forward trigger pulses are supplied, output signals shown in the first chart are repeated every 10 forward trigger pulses so that the signals supplied to the pulse motor from output terminals 0,, 0,, 0,, Q, and Q, through output conductors I, II, lll, 1V and V will change according to a second chart shown in FIG. 3. The second chart shows that two signals l and three signals 1" are obtained alternately to energize two coils and three coils according to the same sequence.

Suppose now that a signal 1" is supplied to reverse signal input conductor F subsequent to forward trigger pulse No. 3 for the purpose of rotating the pulse motor in the reverse direction. lnput terminals connected to reverse signal input conductor R, i.e. even input terminals 20', 4a, 6a, 8a, 10a, 12a, 14a, 16a, 18a and 20a of AU-NAND circuits and even input terminals a 21:, 4b, 6b, 8b, 10b, 12b, 14b, 16b, 18b and 20b of BU-NAND circuits are supplied with signals 1". It is to be remembered that application of trigger pulse No. 3 resul ts tbs generation of outpuLsignalsi l at output terminals 01 Q2, Q3, Q4, Q5, Q8; Q1, 0,, Q, and Q10 and gutppt signals 0 at the output terminals 01, Q1, Q3, 64, 65, Q6, Q 6,, Q, and Q Odd input terminals 50', 7a, 9a, 11a and 13a of AU-NAND circuits and odd input terminals lb, 3b, 15b, 17b and 19b of BU-NAND circuits whic h are associated with output terminals Q4, Qs, Qs, Q1, Q8! Q Q3, Q9. 6, and 6,, respectively, are supplied with signals l." The other odd input terminals la, 3a, 15a, 17a and 19a of AU- NAND circuits and the other odd input terminals Sb, 7 1;, 9b and 13b wh ich are asso ciated v vith output terminals 0,, 0,, Q9, Q Q, Q4, Q Q,, Q, and Q8, respectively, are supplied with signals0."Accordingly, AU-NAND circuits 11A, 13A, 25A, 27A and 29A and BU-NAND circuits 15B, 17B, 19B, 21B and 23B generate signalsl"since they are not simultaneously supplied with signals 1 at their even and odd inputte minals. On the other hand, AU-NAND circuits 15A, 17A, 19A, 21A and 23A and BU-NAND circuits 11B, 13B, 25B, 27B and 29B produce no significant voltage or signal 0" because they are supplied with signals 1" at their even and odd input terminals simultaneously. Furthermore, all AE- NAND circuits 12A, 14A, 16A, 18A, 20A, 22A, 24A, 26A, 28A and 30A and all BE-NAND circuits 12B, 14B, 16B, 18B, 20B, 22B, 24B, 26B, 28B and 30B produce signals l" since odd input terminals 1a, 3a, 5a, 7a, 9a, 11a, 13a, 15a, 17a and 19a of AE-NAND circuits and odd input terminals 1b, 3b, 5b, 7b, 9b, 11b, 13b, 15b, 17b and 19b of BE-NAND circuits are connected to forward signal input conductor F which is not supplied with a signal l at this time. Accordingly, A-AND circuits 1A, 2A, 8A, 9A and 10A and B-AND circuits 3B, 4B, 5B, 6B and 7B generate signals l respectively by the simultaneous application of signals 1" at both of their input terminals, thus applying signals l to associated input terminals K,, K K K K J J J J and J-,. The other A-AND circuits 3A, 4A, 5A, 6A and 7A and the other B-AND circuits 1B, 2B, 8B, 9B and 10B generate signals whereby input terminals K K.,, K K,, J, 1,, J J and J associated therewith are supplied with signals 0. Summarizing the above, when a signal l is applied to reverse signal input conductor R instead of forward signal input conductor F subsequent to the trigger pulse No. 3, input terminals which have received signals 1" are changed from K J and 1,, to J 1,, K and K When a reverse trigger pulse No. l (by the term "reverse trigger pulse"is meant a trigger pulse which is applied to trigger input conductor T while a reverse signal 1 is being applied to reverse signal input conductor R) is applied to trigger input terminals T through T inclusive of the J-K flipflops, J-K flip-flops FF;, and FF,; are switched to produce signals l from their output terminals 0;, and 6 respectively, due to the application of the signals l to input terminals J and K However, the other J-K flip-flops FF FF FF FF FF FF FF,,, and FF will not be reversed since they are supplied with signals which correspond to output terminals producing signals l" At this time, the output signals 1 which are applied to the pulse motor are obtained from output conductors I1, 111 and 1V connected to output terminals Q Q and 0, thus energizing coils 102, 103 and 104 of the motor. Therefore, output signals from output terminals of all J -K flipflops are identical to those generated when a forward trigger No. 2 is applied to forward signal input conductor F. As a result of the application of a reverse trigger pulse No. 1, input terminals of two J-K flip-flops FF and FF, to be supplied with signals l" are changed from K to J and from J, to K, to prepare for a reverse trigger pulse No. 2. Upon application of the reverse trigger pulse No. 2 to trigger pulse input conductor T, .l-K flip-flops FF, and FF, are switched whereby output signals from output terminals of all J-K flip-flops become identical to those generated when the forward trigger pulse No. l was applied to trigger input terminal T and when input terminals J and K were supplied with signals 1" instead of input terminals K and J in this manner, to rotate the pulse motor in the reverse direction the output signals from J-K flipflops are instantly switched back by the reverse trigger pulses without any troubles even if the forward trigger pulse was changed to the reverse trigger pulse in a very short time. FIG. 4 is a third chart showing states of the output signals from output terminals Q through Q inclusive when reverse trigger pulses from No. l to No. 10 are successively applied. These states of output signals are obtained repeatedly every 10 reverse trigger pulses. FIG. 5, is a fourth chart showing the states of output signals appearing at output conductors I, 11, Ill, IV and V connected to output terminals, that is the sequence of energization of the coils provided for the pulse motor shown in FIG. 6. As can be noted from the fourth chart, two coils and three coils are energized alternately and the sequence of the energization is just opposite to that of the second chart shown in FIG. 3.

Referring now to P10. 7, there is shown a modified pulse motor drive system of this invention for controlling an electric pulse motor provided with three coils by alternately energizing one and two thereof. In this'embodiment, flip-flops FF FF FF FF FF, and FF have the same construction and operate in the same manner as flip-flop FF, used in the first embodiment and these flip-flops are provided with output terminals Q51, Q52, Q53, Q Q and Q output Erminals or mplementary output terminals O51 O52, Qsa. Q54, Q55 and Q input terminals 1 J J .1 J and J input terminals or complementary input terminals K K K K K and K set ten'ninals SD SD SD SD SD and SD reset terminals RD RD RD RD RD and RD and trigger input terminals T T T T T and T respectively. A forward signal input conductor Fa is connected to odd input terminals 111a, 113a, 115a, 117a, 119a and 121a of respective AE-NAND gate circuits 112A, 114A, 116A, 118A, 120A and 122A. A reverse signal input conductor Ra is connectedv to even input terminals 112a, 114a, 116a, 118a, 120a, and 122a of respective AU-NAND circuits 111A, 113A, 115A, 117A, 119A and 121A. Output terminals of all AE-NAND circuits are connected to AND circuits 101A, 102A, 103A, 104A, 105A and 106A, respectively. Output terminals AU- NAND circuits 111A, 113A, A, 117A, 119A and 121A are also connected to AND circuits 101A, 102A, 103A, 104A, 105A and 106A, respectively. Furthermore, these AND circuits are respectively connected to input terminals, J and K J and K J and K J and K J and K and J and K to apply output signals thereto. NOT circuits 51C, 52C, 53C, 54C, 55C and 56C are interposed between AND circuit 101A and input terminal J AND circuit 102A and input terminal .1 AND circuit 103A and input terminal J AND circuit 104A and input terminal .1 AND circuit 105A and input terminal J and between AND circuit 106A and input terminal J respectively. Each one of the NOT circuits has the same construction and operation and functions to invert the signal applied by the NAND circuit, that is, it produces an output signal 1" when a signal l is not applied thereto whereas it produces an output signal 0 when a signal l is applied thereto. A trigger input conductor Ta for passing trigger pulses is connected to trigger input terminals T T T T T and T of the J-K flip-flops. An input conductor Res for set and reset signals is connected is connected to set terminals 50 SD and SD of respective flip-flops and to rest terminals RD RD,; and RD of respective flip-flops. Output terminals Q51, O52. O53. Q54, 0 and Q are respectively connected to even input terminals 114a, 116a, 118a, a, 122a and 112a of respective AE-NAND circuits 114A, 116A, 118A, 120A, 122A and 112A and thence to odd input terminals121a', 111a, 115a, 117a and 119a of respective AU- NAND circuits 121A, 113A, 115A, 117A, and 119A. Output terminals Q Q and Q are further connected to an electric pulse motor of the conventional type, not shown, though output conductors I, II and Ill. The pulse motor is provided with three stationary coils and a rotor which is driven by alternately energizing one coil and two coils.

The operation of this modified pulse motor drive system is as follows: Application of a reset pulse signal to reset conductor Res causes J-K flip-flops FF FF and FF to set and the other J-K flip-flops FF FF and FF to reset. in the set and reset conditions, output si nals l" are generated at output terminals 0 O Q Q and 6 of J-K flip-flops whereas output signals 0" are generated at output terminals Q51, Q52, Q53, Q54, Q55 and Q58 thereof. Accordingly, the output signals l appearing at output terminals Q and Q are applied to the pulse motor to energize its two coils through output conductors I and 11. Furthermore, the output signals 1 appearing at output terminals Q Q and Q are applied to even input terminals 114a, 116a and 118a of respective AE NANDcircuits TEXTlbifand 118A, and thence to odd input terminals 121a, llla'and 1l3a'of AU-NAND circuits 121A, 111A and 113A, respectively. While these NAND circuits are in their set and reset conditions, when input signals l and 0" are applied to forward signal input conductor Fa and reverse signal input conductor Ra, respectively, the input signals 1" are supplied to odd input terminals 111a, 113a, 115a, 117a, 119a and 1210 of AE-NAND circuits, respectively. Accordingly, AE-NAND circuits 114A, 116A, and 118A generate signals since these NAND circuits will simultaneously be supplied with signals 1" to their even and odd input terminals. The other AE-NAND circuits 112A, 120A and 122A generate signals l since these NAND circuits will not simultaneously be applied with signals l at both of their input terminals. On the other hand, all AU-NAND circuits 111A, 113A, 115A, 117A, 119A and 121A generate output signals 1" since their even input terminals 112a, 114a, 116a, 118a, 120a and 122a are connected to reverse signal input conductor Ra which is not applied with any significant voltage during the operation of the forward rotation. AND circuits 101A, 105A and 106A which are simultaneously supplied with signals 1" from associated NAND circuits generate signals l which are applied to input terminals K K and K The other AND circuits 102A, 103A and 104A which are supplied with signals l alone from associated AU- NAND circuits 113A, 115A and 117A generate signals 0" whereby NOT circuits 52C, 53C and 54C generate signals l which are applied to input terminals 1 J and J respectively.

Thereafter, when a forward trigger pulse No. l (as above described, the term forward trigger pulse means a trigger pulse applied to trigger input conductor a when a forward signal is being applied to forward signal input conductor Fa is applied to trigger input terminals T T T T T and T output terminals of .l-K flip-flops FF, and FF will be switched to generate signals l from output terminals O5; to Q and output terminals Q to Q respectively, since J-K flip i'lops an are supp re wr signals I at their input terminals K and J respectively. However, the other J- K flip-flops FF FF FF and FF are maintained in their previous conditions since they are supplied with signals l to their input terminals J J K and K to przosduce output signals l" at their output terminals Q Q a and O respectively. Therefore, an output signal l which is applied to the pulse motor having three coils is obtained from output terminal 0,, via output conductor ll. As a result of switching or reversal of flip-flop FF,, the output signal of AND-circuit 102A is changed from 0" to l since the output signal from output terminal 0,, is changed from l to l with a result that NAND circuit 114A generates an output signal "1" which is supplied to AND circuit 102A. Similarly, as a result of the reversal of J-K flip-flop FF the output signal of AND circuit 105A is caused to change from l to 0 whereby NOT circuit 55c supplies signal l to the input terminal .1 since the output signal from the output terminal Q is changed from 0" to l with a result that NAND circuit 120 changes its output signal from l to 0. Upon application of a forward trigger pulse No. 2 upon trigger input terminalsl T T T T and T through trigger input conductor Ta subsequent to the application of a forward trigger pulse No. 1 1-K flip-flops FF and FF are caused to reverse at this time so as to generate output signals 1" at their output terminals 6 and Q respectively whereas the other flip-flops FF FF FF and FF are maintained in the previous states. At this time, the output signals 1" are produced from output terminals Q and Q and are applied to.the pulse motor through output conductors ll and 11!. Input terminals for receiving signals I are changed from input terminals 1,, and to input terminals K and J respectively. In this manner, when a forward trigger pulse is supplied to trigger input conductor Ta, two of HC flip-flops FF FF FF FF FF and FF are reversed and the input terminals of the .l-K flip-flops to the right of the reversed J-K flip-flops are switched to receive signals l to prepare for the reversal caused by a next succeeding forward trigger pulse. Combinations of a single output signal l and two output signals 0 and of a single output signal 0 and two output signals 1 are obtained alternately from output conductors I, II and III to drive the pulse motor having three coils. Upon application of a reverse trigger pulse upon trigger input conductor Ta, two of .l-K flip-flops FF F P FF FF FF and FF are reversed and the input terminals of .I-K flip;flops to the lift of the reversed flip-flops are switched to receive signals 1" to prepare for the reversal caused by a next succeeding reverse trigger pulse. in this manner, output signals are regularly produced by the reverse trigger pulses from output conductors l, ll and III to drive the pulse motor in the reverse direction.

While the invention has been shown and described in terms of preferred embodiments thereof, it should be understood that the invention is by no means limited thereto and that many changes and modifications will be obvious to one skilled in the art without departing from the spirit and scope of the invention.

What is claimed is:

l. A pulse motor drive system for controlling the direction of rotation of a pulse motor having a plurality of driving coils comprising a plurality of flip-flops capable of changing output signals thereof in accordance with input signals supplied to said flip-flops, each one of said flip-flops being provided with a pair of input terminals and at least one output terminal, the number of said flip-flops being twice the number of said driving coils; a plurality of gate circuits interconnecting said flipflops in ring formation and being responsive to output signals from the output terminals of each flip-flop to supply input signals to the input terminals of the next successive flip-flop in accordance with said output signals from the next preceding flip-flop; conductors connected to said output terminal of alternate ones of said flip-flops to supply output signals from said last-mentioned output terminals to said driving coils of said pulse motor;

a reset conductor connected to each of said flip-flops for setting a first half of said flip-flops and for resetting a second half of said flip-flops upon the occurrence of a reset signal;

a trigger input conductor connected to supply trigger pulses to each of said flip-flops to switch output signals of a flipfiop in said first half and a flip-flop in said second half;

a forward signal input conductor connected to said gate circuits to supply a signal for commanding forward rotation of said pulse motor; and

a reverse signal input conductor connected to said gate circuits to supply a signal for commanding reverse rotation of said pulse motor.

2. A pulse motor drive system according to claim 1, wherein each one of said gate circuits comprises a first gate circuit and a second gate circuit,

said first gate circuit including a first NAND circuit, a

second NAND circuitand an AND circuit,

said AND circuit being responsive to output signals from said first and second NAND circuits and capable of supplying signals to the input terminal of one of said flipflops, said first NAND circuit being connected to said forward input conductor and to the output terminal of the next preceding flip-flop, said second NAND circuit being connected to said reverse signal input conductor and to the output terminal of the next succeeding flip-flop, said second gate circuit being provided between said one of said flip-flops and an adjacent flip-flop.

3. The pulse motor drive system according to claim 2, wherein said second gate circuit is similar to said first gate circuit.

4. The pulse motor drive system according to claim 2, wherein said second gate circuit is connected as a NOT circuit between said one of said flip-flops and said AND circuit for inverting output signals from said AND circuit.

Patent No.

Inventor(s) CERTIFICATE OF CORRECTION Dat October 19, 1971 Kuriihiko Eto It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

IN THE PATENT:

Column l, line line line

- line Column 2 line line line

line

- for for "mphase" read --In phase for "input" read cutput-;

for "of lead" read or lead--;

flip-flop circuits;

for "terminals b, 3b, read terminals lb, 3b-;

for "circuits 12B, .20B, 22B, 263" read circuits 1213,...2013, 22B, 2flB, 26B;

for "The terms odd" read The terms "odd,";

for "minals 2a 4a-6a. .and 2051"" read "minals 2a 4a 6a .and 20a'' for "terminals 2b 4b'6b' .and 20b read terminals 2b 4b 6b and 20b';

for "terminals 2a 4a'6a' 8a 10a read terminals 4a 6a l0a' for "circuits l-A, read circuits lA,--

UNITED STATES PA'IENT OFFICE CERTIFICATE OF CORRECTION Patent No. 3, 614,580 Date October 19, 1.971

Invent0r( 'llnlhlko It is certified that error appears in the above-idcntified patent and that said Letters Patent are hereby corrected as shown below:

IITage 2 1 Column 2 continued line 66, for "A A A 'A read A A A A I.

" line 68 for "circuits respective" read circuits are rspectiveline 69, for "E read 13 line 70, omit the conuna in the first instance;

line 70,, for "B 'B 13 read B B B line 71 9 read 9";

Column 3 line 1, for read J line 5, for Q read Q Column 4 line 46, "Q in the first instance should read-6 line 58, for "terminals" read :--termir 1al Column 5 line 1, for "E5 read Q line 5, for "24A (after '0 is supplied" read 241\ is L supplied-; I J

line 43,- for "Q read Q line 44 omit the comma in the first instance;

r -w UNITED STATES PATENT OFFICE r CERTIFICATE OF CORRECTION Patent 3'6l4'580 Dated October 19, 1971 Inventor) Kunihiko Eto It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

Page 3 Column 6 line 63, for "0 in the secend instance, read --Q line '66, r "7b', 9b'" read 7b', 9.16, 11b'--:

Column: 7 line 18, for read --K line 34, f or "signals which" reed ---sig nals "l" at theiI input terminale K1, K2, J4, J5, J6, J7, K9 and Kl0-; 4 t

' line 62, for'-"l0" read -ten- Zolumn 8 line 45, for "llla' 115a read 1118 1143a ll5a;

' line 46, -fo r "121A, 113A" read '--121A, 111A, 113A--;

line 48, for "though" read*-through;

Tolumn 9 line 24, for "conductor Fa" read --con ductor 'F a Signed and sealed this 18th day of Ju1y'1972.

(SEAL) fittest:

' 0 ER 5R. ROBER'T GO'I'TSCHALK EDWARD M FLIET H Commissioner of Patents J Attesting Officer 

1. A pulse motor drive system for controlling the direction of rotation of a pulse motor having a plurality of driving coils comprising a plurality of flip-flops capable of changing output signals thereof in accordance with input signals supplied to said flip-flops, each one of said flip-flops being provided with a pair of input terminals and at least one output terminal, the number of said flip-flops being twice the number of said driving coils; a plurality of gate circuits interconnecting said flipflops in ring formation and being responsive to output signals from the output terminals of each flip-flop to supply input signals to the input terminals of the next successive flip-flop in accordance with said output signals from the next preceding flip-flop; conductors connected to said output terminal of alternate ones of said flip-flops to supply output signals from said last-mentioned output terminals to said driving coils of said pulse motor; a reset conductor connected to each of said flip-flops for setting a first half of said flip-flops and for resetting a second half of said flip-flops upon the occurrence of a reset signal; a trigger input conductor connected to supply trigger pulses to each of said flip-flops to switch output signals of a flip-flop in said first half and a flip-flop in said second half; a forward signal input conductor connected to said gate circuits to supply a signal for commanding forward rotation of said pulse motor; and a reverse signal input conductor connected to said gate circuits to supply a signal for commanding reverse rotation of said pulse motor.
 2. A pulse motor drive system according to claim 1, wherein each one of said gate circuits comprises a first gate circuit and a second gate circuit, said first gate circuit including a first NAND circuit, a second NAND circuit and an AND circuit, said AND circuit being responsive to output signals from said first and second NAND circuits and capable of supplying signals to the input terminal of one of said flip-flops, said first NAND circuit being connected to said forward input conductor and to the output terminal of the next preceding flip-flop, said second NAND circuit being connected to said reverse signal input conductor and to the output terminal of the next succeeding flip-flop, said second gate circuit being provided between said one of said flip-flops and an adjacent flip-flop.
 3. The pulse motor drive system according to claim 2, wherein said second gate circuit is similar to said first gate circuit.
 4. The pulse motor drive system according to claim 2, wherein said second gate circuit is connected as a NOT circuit between said one of said flip-flops and said AND circuit for inverting output signals from said AND circuit. 